Method for the fabrication of a stacked capacitor all in the dyn

Details Method for the fabrication of a stacked capacitor all in the dyn Method for the fabrication of a stacked capacitor all in the dyn

1994-09-07

1995-10-24

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

054609968

ABSTRACT:
A method for the fabrication of semiconductor memory device. The method comprises the processes of forming an MOS transistor having an impurity-diffused region of LDD structure at a semiconductor substrate having a P-well (or N-well) therein, forming a two-layer charge storage electrode in such a manner to come into contact with the impurity-diffused region of the MOS transistor, and sequentially forming a dielectric film and a plate electrode on all exposed areas of the two-layer charge storage electrode. The method forms a two-layer structure of charge storage electrode in a DRAM cell, effecting an increase of effective area in the charge storage electrode and improving the degree of integration in a semiconductor memory device.

REFERENCES:
patent: 5330614 (1994-07-01), Ahn
patent: 5389560 (1995-02-01), Park
Ser. No. 08/273,904 Eui Kyu Ryou Jul. 12, 1994.
Ser. No. 08/294,840 Keum et al. Aug. 29, 1994.
Ser. No. 08.297,759 Keum et al. Aug. 30, 1994.

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