Fishing – trapping – and vermin destroying
Patent
1993-03-25
1995-10-24
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 68, 437913, 437985, 148DIG116, 148DIG126, H01L 218232
Patent
active
054609852
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a vertical type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to be used as a semiconductor device for electric power, which is preferable in the case of adoption as MOSIC and the like in which an elemental article thereof or the semiconductor device for electric power is incorporated.
BACKGROUND ART
The vertical type power MOSFET has many features such that it has excellent frequency characteristics, has a fast switching velocity, can be driven at low electric power and the like, so that it has recently been used in many industrial fields. For example, in "Nikkei Electronics" published by Nikkei-McGraw-Hill, Inc. on May 19, 1986, pp. 165-188, it is described that the focus of development of the power MOSFET is in migrating to low voltage resistant articles and high voltage resistant articles. Further, it is described in this literature that the ON-resistance of a power MOSFET chip having a voltage resistance not more than 100 V has become low up to a level of 10 m.OMEGA., and it is described as a reason thereof that the channel width per area has been able to be made large by utilizing the fine processing of LSI in the production of the power MOSFET, or by improving the shape of its cell. In addition, in this literature, the description is made using the vertical type power MOSFET as a main topic in which a DMOS type (double diffusion type) cell which is in the main current is used. The reason is that the DMOS type is fabricated by the planar process characterized in that the flat main surface of a silicon wafer is exactly used for a channel portion, so that it has advantages in production of a good yield and a cheap cost.
On the other hand, in accordance with popularization of the vertical type power MOSFET, the realization of low loss and low cost is further demanded, however, the reduction in the ON-resistance by the fine processing or the improvement in the shape of the cell has arrived at the limit. For example, according to the official gazette of Japanese Patent Application Laid-open No. Sho 63-266882 (1988), it has been known that the DMOS type has a local minimum point in which the ON-resistance does not further decrease even when the size of the unit cell is made small by fine processing, and a major cause thereof is the increase in the JFET resistance which constitutes a component of the ON-resistance. In addition, with respect to the DMOS type, as shown in the official gazette of Japanese Patent Application Laid-open No. Hei 2-86136 (1990), the size of the unit cell with which the ON-resistance provides the local minimum point is in the vicinity of 15 .mu.m under the present fine processing technique.
In order to break through this limit, various structures have been proposed. The common feature among them is a structure in which a groove is formed on the device surface, and channel portions are formed at side faces of the groove, and owing to this structure, the above-mentioned JFET resistance can be greatly decreased. Further, in the structure in which the channel portions are formed at the side faces of the groove, the increase in the JFET resistance can be neglected even when the unit cell size is made small, so that there is no limit that the ON-resistance provides the local minimum point with respect to the reduction in the unit cell size as described in the official gazette of Japanese Patent Application Laid-open No. Sho 63-266882 (1988), and it can be made small to the limit of the fine processing breaking though 15 .mu.m.
The structure, in which the channel portions are formed at the side faces of the groove, is called the R (Rectangular)-MOS device or the U (U-shaped)-MOS device according to its shape. The structure shown in the official gazette of Japanese Patent Application Laid-open No. Sho 59-8374 (1984) is an example of the R-MOS device, which is a structure alternatively called the trench gate type in which a vertical groove is formed at the device surface by means of the anisotropic dry etching method, and chan
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Takahashi Shigeki
Tokura Norihito
Hearn Brian E.
Ipics Corporation
Trinh Michael
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