Clocked IGFET logic circuit

Details Clocked IGFET logic circuit Clocked IGFET logic circuit

1980-08-18

1982-08-17

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307579, H03K 19003, H03K 19096, H03K 1920, H03K 1716

Patent

active

043451705

ABSTRACT:
A clocked IGFET serial decoder circuit has a precharge transistor with its conduction channel connected between a V.sub.DD supply and an output terminal, a string of transistors with their conduction channels connected in series between the output terminal and a switch ground node and a ground switch transistor with its conduction channel connected between the switch ground node and a V.sub.SS supply. The gates of the transistors of the string receive input signals from clocked input buffers which bias the gates at V.sub.DD during the precharge interval when the precharge transistor is ON and the ground switch transistor is OFF. This allows the parasitic capacitances at the junctures of the transistors in the string to become substantially charged during the precharge interval and thus prevent rapid charge sharing at the output terminal when the circuit is enabled.

REFERENCES:
patent: 3567968 (1971-03-01), Booher
patent: 3702945 (1972-11-01), Faith et al.
patent: 3829710 (1974-08-01), Hirasawa et al.
patent: 3982138 (1976-09-01), Luisi et al.
patent: 3999081 (1976-12-01), Nakajima
patent: 4040015 (1977-08-01), Fukuda
patent: 4061929 (1977-12-01), Asano
Stewart, "High-Density CMOS ROM Arrays", IEEE Journal of Solid-State Circuits, vol. SC-12, No. 5, pp. 502-506; 10/77.

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