Process for making CMOS field-effect transistors with self-align

Details Process for making CMOS field-effect transistors with self-align Process for making CMOS field-effect transistors with self-align

1983-04-05

1984-09-04

Saba, W. G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 29578, 29580, 148 15, 148187, 148190, 156653, 156657, 357 23, 357 42, 357 52, H01L 2122, H01L 21265

Patent

active

044688520

ABSTRACT:
Two patches of silicon nitride are formed above spaced-apart regions of an n-type substrate (2) on an overlying oxide layer (8) of small thickness. Arsenic ions are then implanted through the oxide layer in substrate areas not covered by the patches whereupon one patch (10a) and an adjoining portion of the oxide layer are covered by a masking layer (15) of polycrystalline silicon, leaving unprotected the second patch (10b) and an oxide portion adjacent thereto. The wafer is then bombarded with boron ions, first at a relatively low concentration and high energy level to penetrate the oxide layer as well as the second patch (10b) and then, after an intervening high-temperature heat treatment in a nonoxidizing atmosphere, at a relatively high concentration and low energy level. This results in the formation of a p-well (17) bounded by an n+ guard zone (23) and partly underreaching same, with an exposed area of that guard zone converted to p+ conductivity by the second-stage boron bombardment. A further heat treatment, at a somewhat lower temperature, expands the p+ area into a channel stop (21) of this conductivity type which bounds the p-well (17) but does not significantly encroach upon same. Removal of the polycrystalline silicon layer (15) is followed by the growth and partial removal of an oxide layer (8), by the deposition of polycrystalline silicon on residues (24a, 24b) of that layer to form insulated gates (26a, 26b), and by the formation of respective source and drain areas (30, 32 and 34, 36) on the p-well (17) and on an n-type pedestal (19) bounded by an n+ channel stop.

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Lilen, H., "Principes et Applications des CI/MOS", Editions Radio, Paris, France, 1972, pp. 54-59.

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