Method and apparatus for address disambiguation using address co

Details Method and apparatus for address disambiguation using address co Method and apparatus for address disambiguation using address co

1996-09-30

1998-12-08

Ellis, Richard L.

G06F 938

Patent

active

058482563

ABSTRACT:
A scheduling unit is described for scheduling an execution order of a first instruction of a first type and a second instruction of a second type in an instruction stream where the second instruction precedes the first instruction. The scheduling unit comprises a table that records address component identifiers corresponding to the second instruction. An address comparator is coupled to the table. The address comparator compares address component identifiers that corresponds to the first instruction with address component identifiers on the table. The scheduling unit schedules the first instruction to be executed ahead of the second instruction when the address component identifiers differ from the address component identifiers on the table.

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