1980-10-14
1982-11-23
Atkinson, Charles E.
Excavating
371 51, G06F 1110, G11C 2900
Patent
active
043609155
ABSTRACT:
Apparatus and method are provided for isolating errors in a logic system employing memory and having a data transmission bus structure. A memory readout error is detected in a multibit word having a parity bit added thereto by parity checking means. A readout error, commonly referred to as a "soft read error," is an erroneous output from a memory device that is transient in nature in that the soft read error is corrected when the memory device is refreshed or reread. It is contemplated that such a readout error may take place when a multibit word is outputted from a refresh type random access memory such as a dynamic random access memory (RAM) or a write after read core memory. In response to the detection of an error condition in the memory by the parity bit error detector, the memory is read again in order to obtain a second output. If the second output provided by the memory does not contain a parity error, the prior error is considered to be a soft read error and the second data word is forwarded to a utilization device such as a CPU. If the second output from the memory also contains a parity error, such an error is considered to be a "hard read error" and the data is not utilized. Information relating to a parity error occurring in the memory which is not a soft read error is stored for diagnostic purposes. Parity of the data is again checked at the utilization device in order to determine if the transmission means used to transfer the data from the memory to the utilization device has caused a data error. Means of inducing parity errors to test the parity detection circuitry and means to override parity checking are also provided.
REFERENCES:
patent: 3273120 (1966-09-01), Dustin et al.
patent: 3814922 (1974-06-01), Nibby et al.
patent: 3868647 (1975-02-01), Zand veld
patent: 4037091 (1977-07-01), Buescher
patent: 4049956 (1977-09-01), Van Veen
patent: 4051355 (1977-09-01), Lin
patent: 4100403 (1978-07-01), Eggenberger et al.
patent: 4209846 (1980-06-01), Seppa
Cramer and Elmer, Controlled Retry on Storage Errors, IBM Technical Disclosure Bulletin, vol. 11, No. 9, Feb. 1969, pp. 1100-1101.
Helwig et al., Error Correction Without Use of Error-Correction Code, IBM Tech. Disclosure Bulletin, vol. 15, No. 2, Jul. 1972, p. 503.
Atkinson Charles E.
Massung Howard G.
The Warner & Swasey Company
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