Monolithically integrated thermal shut-down circuit including a

Details Monolithically integrated thermal shut-down circuit including a Monolithically integrated thermal shut-down circuit including a

1984-02-22

1985-11-12

Beha, Jr., William H.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307296R, 307310, 323315, 361103, H03K 1730

Patent

active

045530483

ABSTRACT:
A thermal shut-down circuit is provided that is monolithically integrated in a power BIMOS process wherein a vertical power PNP output transistor comprises a P-type substrate as a collector. The circuit compensates for vertical currents injected from the P-substrate into lateral transistors. A first PNP transistor has an emitter connected to a first resistor and conducts a first current. A second PNP transistor has an emitter connected to a second resistor and conducts a second current. A third resistor has one terminal coupled to the emitter of the second transistor. A fourth resistor is coupled in series with an output means, the combination thereof being coupled in parallel with the second and third resistors.

REFERENCES:
patent: 4004462 (1977-01-01), Dobkin
patent: 4028564 (1977-06-01), Streit et al.
patent: 4146903 (1979-03-01), Dobkin
patent: 4204133 (1980-05-01), Ahmed
Schade, "Themal Shutdown Circuit", RCA Tech. Note No. 1270, 3 Sheets, Mar. 2, 1981.

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