Method of making I.sup.2 L heterostructure bipolar transistors

Details Method of making I.sup.2 L heterostructure bipolar transistors Method of making I.sup.2 L heterostructure bipolar transistors

1986-12-01

1988-05-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 32, 437234, 437126, 437133, 437 31, 148DIG11, H01L 2120

Patent

active

047450851

ABSTRACT:
A process of making an integrated injection logic (I.sup.2 L) semiconductor structure is disclosed which is particularly advantageous for implementation in a group III-V compound semiconductor such as gallium arsenide. By use of "regrowth" techniques, the base region of the lateral transistor is made extremely thin (less than one-tenth micron). Utilization of a Schottky collector in a vertical transistor simplifies the structure.

REFERENCES:
patent: 4072545 (1978-02-01), De La Moneda
patent: 4160988 (1979-07-01), Russell
patent: 4550491 (1985-11-01), Pepey

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