Method of manufacturing a vertical semiconductor device

Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure

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438135, 438268, 438710, H01L 21332

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057803242

ABSTRACT:
A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

REFERENCES:
patent: 4412378 (1983-11-01), Shinada
patent: 4731343 (1988-03-01), Beinvogi
patent: 4735824 (1988-04-01), Yamabe
patent: 5385852 (1995-01-01), Oppermann et al.
patent: 5460985 (1995-10-01), Tokura et al.
patent: 5532179 (1996-07-01), Chang et al.
Wolf et al., "Silicon Processing for the VLSI Era", vol. 1, 1986, pp. 539-583.
Chang et al., "Self-Aligned UMOSFET's with a Specific On-Resistance of 1 m.OMEGA. cm.sup.2 " IEEE Transactions on Electron Devices, vol. ED-34, No. 11, Nov. 1987, pp. 2329-2334.
Nikkei Electronic May 1986, No. 395, pp. 165-188.
Lee Y H et al: "Silicon Doping Effects in Reactive Plasma Etching," Journal of Vacuum Science & Technology B (Microelectronics Processing and Phenomena), Mar.-Apr. 1986, USA, vol. 4, No. 2, ISSN 0734-211X, pp. 468-475, XP002006301.
Gill M D: "A Simple Technique for Monitoring Undercutting in Plasma Etching", Solid-State Electronics, Sep. 1980, UK, vol. 23, No. 9, ISSN 0038-1101, p. 995 XP002006201.
N. Tokura et al "The DMOS Consisting of Channel Region Defined by LOCOS (LOCOS-DMOS): A New Process/Device Technology for Low On-Resistance Power MOSFET,"5th International symposium on Power Semiconductor Device and ICs,May 18-20, 1993.
N. Tokura et al., Concave-DMOSFET: A New Super Low on-Resistance Power MOSFET,: The 1994 International Conference on solid State Devices and Materials, Yokohama, Aug. 23-25, 1994.
H. Sakai et al., Methods to Improve the surface Planarity of Locally Oxidized Silison Devices,: J. electrochem.Soc.:Solid-State Science and Technology, vol. 124, No. 2, Feb. 1977,pp. 318-320.
N. Tokura et al., Concave-DMOSFET: A New Super-Low on-Resistance Power MOSFET,: Japanese Journal of Applied Physics, vol. 34 No. 2B, Feb. 1995,pp. 903-908.
"Developint Power MOSFET of 50m.OMEGA.mm," Nikkei Electronics, Sep. 5, 1994, (No.616). pp, 15-16.

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