Lead arrangement for reducing voltage variation

Details Lead arrangement for reducing voltage variation Lead arrangement for reducing voltage variation

1986-04-21

1988-05-31

James, Andrew J.

357 71, 357 45, H01L 2952, H01L 2710

Patent

active

047484942

ABSTRACT:
A semiconductor device includes a plurality of circuit groups constituting an integrated circuit and each constituted by a plurality of circuit blocks and a bias circuit which applies a bias potential to said circuit blocks. The device further includes a plurality of power buses provided above the circuit groups through an insulating layer so as to feed power to circuit elements in the circuit groups. At least one of the power buses is constituted by a first bus for feeding power to the circuit groups and a plurality of second buses respectively provided for the circuit groups so that each second bus receives power from the first bus and feeds power to circuit elements in the corresponding circuit group. Each of the second buses is connected to the first bus at a predetermined position on the corresponding circuit group.

REFERENCES:
patent: T100501 (1981-04-01), Balyoz et al.
patent: 3808475 (1974-04-01), Buelow et al.
patent: 4475119 (1984-10-01), Kuo et al.
patent: 4499484 (1985-02-01), Tanizawa et al.
patent: 4583111 (1986-04-01), Early

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