System to reduce latency for real time interrupts

Details System to reduce latency for real time interrupts System to reduce latency for real time interrupts

1994-12-16

1996-07-09

Heckler, Thomas M.

395739, G06F 946

Patent

active

055353800

ABSTRACT:
A system for providing a time-based interrupt signal to a processor for executing a real time interrupt event with reduced interrupt latency, involves: a first programmable counter, which is capable of interrupting the processor by generating an interrupt signal on a regular time period based on the decrementing of an initial count value loaded therein, which value is re-loaded in the counter when the count is exhausted and the interrupt signal is generated; one or more second programmable counters, also having initial count values loaded therein that are decremented, and each of which, if the count is exhausted before that of the first counter, will not allow certain types of instructions or events, respectively associated with each second counter, to execute, if the execution of such instructions or events would cause an unwanted latency in the interrupt caused by the interrupt signal from the first counter.

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"Method for Controlling the Hardware Level Zero Timer Value for an IBM PC Application", R. Grafe et al. IBM Tech. Dis. Bulletin, Vol. 29, No. 8, Jan. 1987.

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