Digital information error correcting apparatus for single error

Details Digital information error correcting apparatus for single error Digital information error correcting apparatus for single error

1994-05-23

1996-07-09

Baker, Stephen M.

Excavating

371 376, G06F 1110

Patent

active

055352278

ABSTRACT:
Digital information error correcting apparatus for the correction of single errors (SEC), the detection of double errors (DED) and multiple single byte errors (SBD) and the correction of an odd number of single byte errors (ODDSBC) comprising a syndrome generator with generation matrices constituted by the juxtaposition of a plurality of non-zero and distinct submatrices having b rows and r columns where b is the number of bits per byte and r (r.gtoreq.b+2) is the number of syndrome and error check bits, each constituted by an identity submatrix Ib having b rows and columns, vertically aligned over a matrix H having r-b rows and b columns formed by an even number .gtoreq.2 of rows of all 1 elements and the remaining rows being all 0 elements.

REFERENCES:
Fujiwara, E., et al, "Rotational Byte Error Detecting Codes for Memory Systems", Trans. IECE of Japan, vol. E64, No. 5, May 1981, pp. 342-349.
European Search Report.

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