ESD protection circuit and method for BICMOS devices

Details ESD protection circuit and method for BICMOS devices ESD protection circuit and method for BICMOS devices

1994-09-22

1996-07-09

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

361111, 330207P, 330298, 257357, 257360, H02H 320, H02H 902

Patent

active

055350860

ABSTRACT:
An ESD protection circuit for a BICMOS IC device protects NMOS transistors (Q2) of internal CMOS gates (G2) from ESD events at a high potential power rail (VCC). Specifically the ESD protection circuit protects NMOS pulldown transistors coupled between a pullup bipolar emitter follower transistor (Q5) and the low potential power rail (GND). A PMOS current control transistor (QPESD) is coupled with primary current path between the high potential power rail (VCC) and the bipolar emitter follower transistor (Q5) for controlling current flow through the emitter follower transistor. An RC time constant circuit (R10,C1) is coupled between the high potential power rail (VCC) and low potential power rail (GND). The RC time constant circuit is constructed with a time constant for following power up events but not for following the faster ESD events at the high potential power rail. An inverting gate (G2A) is coupled between the control gate node of the PMOS current control transistor (QPESD) and the RC time constant circuit (R10,C1) for turning off the PMOS current control transistor (QPESD) during an ESD event at the high potential power rail. The PMOS current control transistor (QPESD) thereby protects NMOS transistors (Q2) of internal CMOS gates (G2) coupled to the pullup emitter follower transistor (Q5).

REFERENCES:
patent: 4636825 (1987-01-01), Baynes
patent: 4875130 (1989-10-01), Huard
patent: 5105328 (1992-04-01), Schoofs

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