Patent
1996-10-10
1998-06-30
Treat, William M.
395386, 395379, 395388, 395567, G06F 700
Patent
active
057747377
ABSTRACT:
In a variable word length VLIW-instruction processor, a VLIW-instruction word length register is provided. A VLIW-instruction contains an indication as to VLIW-instruction word length such as a VLIW-instruction word length rewrite instruction. Based on this instruction, the VLIW-instruction word length of the VLIW-instruction word length register is rewritten. For the case of normal instructions (object programs) without any indication of the VLIW-instruction word length, a VLIW-instruction word length that is stored in the VLIW-instruction word length register is initialized to a predetermined value by, for example, the loading of an initial program performed at the time of power-on. This initialized instruction word length is used as a fixed value and an object program for a conventional processor is executed. Accordingly, even when the number of instructions that are simultaneously executed is set low, "NOP (non-execution)" is lessened and the effective use of instruction memory becomes possible. In addition, it becomes also possible to run object programs for conventional processors.
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Matsushita Electric - Industrial Co., Ltd.
Patel Gautam R.
Treat William M.
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