Method and apparatus for controlling a response timing of a targ

Details Method and apparatus for controlling a response timing of a targ Method and apparatus for controlling a response timing of a targ

1996-08-09

1998-06-30

Harvey, Jack B.

395309, 395281, 395848, 395842, G06F 946

Patent

active

057746818

ABSTRACT:
A PCI-ISA bridge device includes a PCI interface for driving a target ready signal line when PCI-ISA bridge device is address-specified as a current target by a read cycle on a PCI bus, and a status register for setting status information indicating respective states of a plurality of DMA request signals inputted to DMA controller. Further the PCI interface circuit includes a wait control circuit for inserting a predetermined wait time period in the timing for driving the target ready signal line, when the transaction is a read cycle for reading the content of the status register.

REFERENCES:
patent: 5673400 (1997-09-01), Kenny
Intel Corporation, "Mobile PC/PCI DMA Arbitration and Protrocols MHPG Architecture Functional Architecture Specification," Rev. 2.2, Apr. 22, 1996, pp. 2-27.
Intel Article, "Peripheral Components," pp. 3-33 through 3-50, (1993). PCI Local Bus Specification, PCI Special Interest Group, Revision 2.0 (1995).
PCI Local Bus Specification, PCI Special Intrest Group, Revision 2.1 (1995) .

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