Integrated circuit with anti latch-up circuit in complementary M

Details Integrated circuit with anti latch-up circuit in complementary M Integrated circuit with anti latch-up circuit in complementary M

1991-10-10

1992-06-30

Prenty, Mark

357 41, 357 15, H01L 2702, H01L 2948

Patent

active

051268167

ABSTRACT:
Integrated circuit having anti latch-up circuit in complementary MOS circuit technology. Due to the incorporation of non-linear elements between the ground (V.sub.ss) and the p-conductive semiconductor substrate (P.sub.sub) and between the supply voltage (V.sub.DD) and the n-conductive semiconductor zone (N.sub.w), the risk of the occurrence of the latch-up effect triggered by the build-up of base charges at the parasitic vertical and lateral bipolar transistors is diminished. The space requirement for the non-linear elements to be additionally incorporated is low and the circuit properties of the MOS transistors are not influenced as a result thereof. The realization of the non-linear elements can ensue with Schottky contacts or with additional MOS transistors that are wired as diode elements. A realization in the form of buried diodes of polycrystalline silicon (PSi) is also possible, realized, for example, as barrier layer diodes.

REFERENCES:
"Integrierte MOS Schaltungen", Healbleiterelektronik 14, H. Weiss, pp. 109-112, 1982.
"Static & Transient Latch-UP Hardness in N-Well CMOS with On-Chip Substrate Bias Generator", IEDM85, Technical Digest, D. Takacs, 1985, pp. 504-508.
"A VLSI Suitable Schottky-Barrier CMOS Process", S. E. Swirhun et al., IEEE Transaction on Electron Devices, vol. ED-32, No. 2, Feb. 1985, pp. 194-202.
Lin et al., "Shielded Silicon Gate Complementary MOS Integrated Circuit," IEEE Transactions on Electron Devices, vol. Ed. 19, No. 11, Nov. 1972, pp. 1199-1206.
Dingwall, "Improved COS/MOS Inverter Circuit for Reducing Burn-out and Latch-up," RCA Technical Notes, TN No. 1230, Jul. 1979, pp. 1-4.
E. E. Moore, "Performance Characteristics of RCA's Low-Voltage COS/MOS Devices," Advances in MOS Technology-Session 4B, Paper 4B.3, 1971, pp. 188-189.

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