Cyclic code check bits generation and error correction using sum

Details Cyclic code check bits generation and error correction using sum Cyclic code check bits generation and error correction using sum

1995-10-10

1998-06-30

Baker, Stephen M.

Excavating

371 376, H03M 1300

Patent

active

057744807

ABSTRACT:
Check bits for a cyclic code are generated for a binary integer by first obtaining a remainder value for each bit of the integer resulting from dividing the bits of the integer by a cyclic generator polynomial to obtain a quotient and said remainder. All remainders are then summed modulo 2 to obtain an integer remainder which functions as the cyclic code for the binary integer. An error in a received integer can be identified and corrected by generating new cyclic code check bits for the received integer, and then comparing the new cyclic code check bits to the received cyclic code check bits. Any difference between the two check bits will correspond to the unique remainder for an erroneous bit, which can then be corrected by complementing the bit. If two or more errors are present, an error will be recognized but the specific errors cannot be identified. The integer must then be discarded. In a preferred embodiment the remainder values are added in an exclusive OR circuit in which remainder values for adjacent bits are summed, and adjacent sums are summed to obtain a final remainder value for all bits.

REFERENCES:
patent: 4065752 (1977-12-01), Goldberg
patent: 4623999 (1986-11-01), Patterson
patent: 5282215 (1994-01-01), Hyodo et al.
patent: 5402429 (1995-03-01), Stessens
Ramabadran et al., "A Tutorial on CRC Computations", IEEE Micro, Aug. 1988, pp. 62-74.
Johnston et al., "The ATM Layer Chip: An ASIC for B-ISDN Applications", IEEE J. on Selected Areas in Communications, vol. 9, No. 5, pp. 741-750, Jun. 1991.
Maniatopoulos et al., "Single-Bit Error-Correction Circuit for ATM Interfaces", Electronics Letters, vol. 31, No. 8, pp. 617-618, Apr. 1995.

Affiliated with

Also associated with

Rating

Cyclic code check bits generation and error correction using sum does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cyclic code check bits generation and error correction using sum, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cyclic code check bits generation and error correction using sum will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1867919