State capture/reuse for verilog simulation of high gate count AS

Details State capture/reuse for verilog simulation of high gate count AS State capture/reuse for verilog simulation of high gate count AS

1996-03-08

1998-06-30

Teska, Kevin J.

Boots, shoes, and leggings

395500, G06F 1520

Patent

active

057743800

ABSTRACT:
A Verilog simulation method significantly reduces scenario execution time of very large scale integrated (VLSI) logic models that contain high numbers of sequential devices. A computer implemented method saves the state of sequential devices into a file at a chosen point in a simulation scenario and then inputs this file to initialize another simulation scenario. The method has the ability to utilize the user defined primitive (UDP) model data for the sequential devices present in the technology library. However, using the standard data structure available in the programming language interface (PLI), it is not possible to uniquely identify individual UDPs. UDPs have the characteristic of having only one output each. Therefore, it is possible to uniquely identify each UDP by the net name which is connected to this output. An exception to this is the situation where two or more like-named UDP outputs are connected to the same net. This is not considered a problem to this implementation, since the simulation execution will resolve the nets to one value (no checking is required).

REFERENCES:
patent: 5146460 (1992-09-01), Ackerman et al.
patent: 5274574 (1993-12-01), Tsujido et al.
patent: 5327361 (1994-07-01), Long et al.
patent: 5404496 (1995-04-01), Burroughs et al.
patent: 5455929 (1995-10-01), Bosshart et al.
patent: 5539680 (1996-07-01), Palnitkar et al.

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