Process for fabricating MOS LDD transistor with pocket implant

Details Process for fabricating MOS LDD transistor with pocket implant Process for fabricating MOS LDD transistor with pocket implant

1995-11-13

1996-07-09

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 41, 437 44, 257344, 257345, H01L 218234

Patent

active

055344470

ABSTRACT:
A process for fabricating MOS transistor devices on a semiconducting substrate first forms a shielding layer, having an opening with sidewalls therein, over the substrate to define a channel region. Then, first sidewall spacers are formed on the sidewalls and a gate insulating layer is formed within the confinement of the first sidewall spacers. Next, a gate electrode is formed over the gate insulating layer, and then the first sidewall spacers are removed, thereby forming trenches between the edges of the gate electrode and the shielding layer. Afterwards, lightly-doped regions of a second conductivity type are formed beneath the trenches and doped regions of the first conductivity type are formed to surround the lightly-doped regions. After removing the shielding layer, second sidewall spacers are formed to overlie the lightly-doped regions. Finally, heavily-doped regions of the second conductivity type are formed in the substrate adjacent to both the lightly-doped region and the doped region of the first conductivity type. This fabrication procedure ensures that the junction capacitance is kept low to improve the operational speed characteristics of the MOS transistor.

REFERENCES:
patent: 5082794 (1992-01-01), Pfiester et al.
patent: 5374575 (1994-12-01), Kim et al.
patent: 5389557 (1995-02-01), Jung-Suk
patent: 5434093 (1995-07-01), Chau et al.
patent: 5472897 (1995-12-01), Hsu et al.
patent: 5484743 (1996-01-01), Ko et al.

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