BI-MOS semiconductor integrated circuit

Details BI-MOS semiconductor integrated circuit BI-MOS semiconductor integrated circuit

1991-04-19

1992-06-30

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307570, H07K 19003

Patent

active

051265958

ABSTRACT:
A P-channel MOSFET includes a gate for receiving an input signal, a source connected to a power supply terminal to which a high power supply voltage is applied, and a drain connected to the base of an NPN bipolar transistor at an output stage. The collector of the bipolar transistor is connected to the power supply terminal and the emitter thereof is connected to an output terminal. An N-channel MOSFET includes a gate for receiving the input signal, a drain connected to the output terminal, and a source and a back gate both connected to the base of an NPN bipolar transistor at the output stage. The collector of the bipolar transistor is connected to the output terminal, and the emitter thereof is connected to a power supply terminal to which a power supply voltage of ground potential is applied.

REFERENCES:
patent: 4694203 (1987-09-01), Uragami et al.
patent: 4703203 (1987-10-01), Gallup et al.
patent: 4769561 (1988-09-01), Iwamura et al.
patent: 4879480 (1989-11-01), Suzuki et al.
patent: 4880998 (1989-11-01), Ueda
patent: 4985645 (1991-01-01), Tsutsui

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