Boots – shoes – and leggings
Patent
1989-07-26
1992-01-28
Heckler, Thomas M.
Boots, shoes, and leggings
36493141, 3649353, 3649356, 3649291, 364DIG1, 364DIG2, G06F 1338
Patent
active
050848364
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a parallel signal processing system in which an input signal is divided to a plurality of sub-signals each of which is processed in parallel, and the resultant parallel signals are read out in a short time.
BACKGROUND OF THE INVENTION
When a signal, such as a picture signal which has a large amount of information, is processed at high speed, it is advantageous to separate the signal to be processed into a plurality of sub-signals, each of which is processed in parallel at the same time, and to read out the processed outputs of each separated sub-signal in a short time.
FIG. 3 shows a prior parallel signal processing system. The following description is directed to the final stage of the parallel signal processing to read out the separated parallel results stored in each parallel memory.
In the figure, the numeral 1 (1a-1n) is a signal processing element (called a processor hereinafter) for processing a plurality of separated sub-signals, 2 (2a-2n) is a memory for storing the signal processed by the processor 1, 3 is an address bus for coupling the processor 1 and the memory 2 by an address line (A), a data line (D) and a control line (C), 4 is a host processor for controlling a plurality of element processors, 5 is a selector for selecting the element processor to be connected to the host processor according to the control of the host processor 4, and 6 is a processor unit which includes an element processor 1 and a memory 2. Eight processor units (n=8) are coupled with one another in parallel in the embodiment of FIG. 3.
When the output signals, processed by each processor units 6, are read out, a port of each element processor 1 is selected by the selector 5 sequentially, and the signals in the memories are transferred to the host processor according to the handshake protocol.
However, the prior system has the disadvantages that the signal transfer speed is only 1.5 Mbit/sec (700 nsec) in the typical embodiment, and it takes considerable time to switch the element processors which are the information source. Therefore, when the number of processors 1 in parallel increases, it takes a long time to read out the resultant output signals and the real time, read out is impossible, although the signal processing capability increases. Although a prior direct memory access system would be useful to read out the output signals quickly, the control of that system would be very complicated when the number of parallel processor units 6 is large, and therefore, the total processing speed of the parallel signals decreases.
SUMMARY OF THE INVENTION
The object of the present invention is to overcome the disadvantages of a prior system, and to provides a parallel signal processing system which processes parallel signals with high speed.
The feature of the present invention is a parallel signal process system comprising a plurality of processor units each having a processor for processing a signal which is divided to a plurality of sub-signals, and a memory coupled with the processor through an internal bus for storing results processed by the processor. A host processor controls the plurality of processor units. The host processor reads out signals which are processed by the plurality of processor units in parallel. A first bus couples the processor with the memory. A second bus couples adjacent processor units. A first switch switches the first bus and the second bus. A second switch switches direction of the second bus. The first switch and the second switch are switched so that signals processed by the plurality of processor units are read out with high speed by the host processor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the parallel signal processing system according to the present invention,
FIG. 2 is a block diagram of the transparent memory according to the present invention, and
FIG. 3 is a block diagram of a prior parallel signal processing system.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The embodiments of the present in
REFERENCES:
patent: 4204251 (1980-05-01), Brudevold
Heckler Thomas M.
Kokusai Denshin Denwa Co. Ltd.
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