Method for forming low resistance DRAM digit-line

Details Method for forming low resistance DRAM digit-line Method for forming low resistance DRAM digit-line

1991-07-01

1992-01-28

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 48, 437200, 437228, H01L 2170

Patent

active

050844067

ABSTRACT:
A DRAM fabrication process is disclosed for constructing a reduced resistance digit-line. The digit-line is so constructed as to maintain low resistance as it crosses the gaps between word-lines. By bridging gaps having a dimension less than or falling below a calculated critical gap spacing, and following the contours of gaps having a dimension greater or falling above that critical gap dimension, the digit-line resistance can be minimized.

REFERENCES:
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patent: 4970564 (1990-11-01), Kimura et al.
Kimura et al., "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-Line Structure", IEDM Digest, 1988, pp. 596-599.
Toru Kaga et al., "Crown Shaped Stacked Capacitor Cell for 1.5 V Operation 64-Mb DRAMS", IEEE Trans. on Electron Dev., vol. 38, No. 2-Feb. 1991, pp. 225-226.
S. Inoue et al., "A Stacked Capacitor (SSC) Cell for 64 mBit DRAMS", IEDM Digest, Dec. 89, pp. 31-34.
T. Kisu et al., "A Novel Storage Capacitance Enlargement Structure Using a Double Stacked Storage Node in STC DRAM Cell", Conf. on Solid State Materials and Dev., 1988, pp. 581-584.
Y. Kawamoto et al., "A 1.28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64 mb DRAMS", Symposium on VLSI Technology, 1991, pp. 13-14.
T. Ema et al., "3-Dimensional Stacked Capacitor Cell for 16m and 64M Drams", IEDM Digest, 1988, pp. 592-595.
Hideo Watanabe et al., "Stacked Capacitor Cells for High-Density Dynamic RAM", IEDM Digest, 1988, pp. 600-603.

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