Method for determining functional equivalence between design mod

Details Method for determining functional equivalence between design mod Method for determining functional equivalence between design mod

1997-03-03

1998-05-19

Trammell, James P.

Boots, shoes, and leggings

364491, 395500, 371 221, 371 271, 371 274, G06F 1750

Patent

active

057544549

ABSTRACT:
The present invention determines whether two design files have identical functionality by attempting to create a binary decision diagram (BDD) for corresponding verification output pairs(302). When the BDD creations are not successful for all evaluated output pairs a set of cutpoint pair candidates are identified(303). An automatic test program generator (ATPG) is used to determine whether or not the cutpoint pair candidates are invalid cutpoints(304). The invalid cutpoints are removed from the set of cutpoint pair candidates(305). A cutpoint pair candidate having known support is selected(306). An exclusive-or of the outputs of the selected candidate is formed (307). A BDD for the resulting XOR function is attempted (308). If a BDD having a zero or one value is built then the selected candidate is valid indicating equivalence (310). If the BDD is neither the zero function nor the one function, the cutpoint pair is invalid if all of its inputs are verification inputs (311). If one or more of the inputs are cutpoint variable inputs, the function for a cutpoint variable input is substituted (309), and the flow continues to build a new BDD for the evaluation XOR having the substituted function.

REFERENCES:
patent: 5331568 (1994-07-01), Pixley
patent: 5572535 (1996-11-01), Pixley et al.
patent: 5649165 (1997-07-01), Jain et al.
Masahiro Fujita, et al., "Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams", 1988 IEEE, CH2657-5/88, 4 pgs.
Yusuke Matsunaga, "An Efficient Equivalence Checker for Combinational Circuits", 33rd Design Automation Conf., ACM 0-8979-1-779-0/96/0006, pp. 629-634.
C. Leonard Berman, et al., "Functional Comparison of Logic Designs for VLSI Circuits", 1989 IEEE, CH2805-0/89/0000/0456, pp. 456-459.

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