Method and apparatus for reducing bleed currents within a DRAM a

Details Method and apparatus for reducing bleed currents within a DRAM a Method and apparatus for reducing bleed currents within a DRAM a

1998-08-20

2000-06-20

Nelms, David

Static information storage and retrieval

Powering

365227, G11C 800

Patent

active

060785381

ABSTRACT:
A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

REFERENCES:
patent: 5235550 (1993-08-01), Zagar
patent: 5552739 (1996-09-01), Keeth et al.
patent: 5557579 (1996-09-01), Raad et al.
patent: 5732033 (1998-03-01), Mullarkey et al.

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