Microcomputer system for high speed address translation

Details Microcomputer system for high speed address translation Microcomputer system for high speed address translation

1987-06-25

1989-04-04

Fears, Terrell W.

Static information storage and retrieval

Addressing

364200, G11C 800, G06F 900

Patent

active

048192112

ABSTRACT:
An address information line of a microprocessor informs a memory management unit of such address information that a current address is identical to an address before one bus-cycle or two bus-cycles or is a new address. Since the address information line has a light load, the address information is transmitted at high speed. In addition, if the current address is identical to the address before one or several bus-cycles, address conversion within the memory management unit can be quickened in such a way that these addresses are temporarily stored in the memory management unit, whereupon the corresponding address is read out.

REFERENCES:
patent: 4438489 (1984-03-01), Heinrich et al.
patent: 4532606 (1985-07-01), Phelps
patent: 4680701 (1987-07-01), Cochran
patent: 4706219 (1987-11-01), Miyata et al.
Cohen et al., IEEE Micro, Apr. 1986, pp. 13-16, "The Design and Implementation of the MC68851 Paged Memory Management Unit".

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