Address enable circuit in synchronous SRAM

Details Address enable circuit in synchronous SRAM Address enable circuit in synchronous SRAM

1997-05-02

1998-12-08

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365195, 36523006, 365233, 365194, G11C 800

Patent

active

058480226

ABSTRACT:
A novel address enable circuit for use in a synchronous memory that includes a memory core. The address enable circuit includes an address latching circuit that outputs a synchronized address and latches a pre-decoded address when an input clock signal transitions from a first logical level to a second logical level so that the synchronized address identifies the pre-decoded address. The address enable circuit also includes a reset circuit that generates a reset signal that (1) does not indicate a reset when the latched chip enable signal indicates that the memory has been selected while the clock signal is at the second logical level, (2) indicates a reset when the latched chip enable signal indicates that the memory has not been selected while the clock signal is at the second logical level, and (3) does not indicate a reset while the clock signal is at the first logical level. The address latching circuit is reset when the reset signal indicates a reset so that the synchronized address identifies a disabled address that indicates that memory access to the memory core is disabled and is not reset when the reset signal does not indicate a reset.

REFERENCES:
patent: 5596537 (1997-01-01), Sukegawa et al.
patent: 5748553 (1998-05-01), Kitamura

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