Integrated circuit with MOS capacitor for improved ESD protectio

Details Integrated circuit with MOS capacitor for improved ESD protectio Integrated circuit with MOS capacitor for improved ESD protectio

1992-04-09

1993-11-23

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257534, 257535, 257297, H01L 2702

Patent

active

052647234

ABSTRACT:
A MOS capacitor, with the polysilicon gate level as one plate, the gate oxide as the insulator, and the underlying semiconductor tub region as the other plate, is used to increase electrostatic discharge (ESD) protection. In an illustrative embodiment, wherein the substrate is n-type and the tub is p-type, the polysilicon level is connected to the negative power supply voltage conductor (V.sub.SS), and the underlying semiconductor region is connected to the positive power supply conductor (V.sub.DD). Since the tub region is p-type, an accumulation-type capacitor is formed. Surprisingly, the thin gate oxide is sufficient to withstand the high ESD voltages, with the protection increasing in one design from less than 1000 volts without the capacitor to 2000 volts with the capacitor.

REFERENCES:
patent: 4806999 (1989-02-01), Strauss
patent: 4821089 (1989-04-01), Strauss
patent: 4990802 (1991-02-01), Smooha
patent: 5032892 (1991-07-01), Chern et al.
"The Dynamic of Electrostatic Discharge Prior to Bipolar Action Related Snap-Back", by Gadi Krieger, VLSI Tichnology Inc., 1101 McKay Dr., San Jose, Calif. 95131, 1989 EOS/ESD Symposium Proceedings, p. 136 through 144.

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