Memory array having a multi-state element and method for forming

Details Memory array having a multi-state element and method for forming Memory array having a multi-state element and method for forming

1999-02-05

2000-06-20

Bowers, Charles

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

257 3, H01L 4500

Patent

active

06077729&

ABSTRACT:
A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at least a portion of the plurality of electrodes. The electrodes can be contacts, plugs or pillars deposited in etched openings in the dielectric volume.

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