Signaling protocol for concurrent bus access in a multiprocessor

Details Signaling protocol for concurrent bus access in a multiprocessor Signaling protocol for concurrent bus access in a multiprocessor

1994-01-14

1995-06-20

Shin, Christopher B.

Boots, shoes, and leggings

395275, 395725, 364240, 364229, 3642306, 364DIG1, G06F 1300

Patent

active

054267404

ABSTRACT:
An improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access. This reduces the system bus idling time without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase. The improved bus architecture uses a system generated I/O bus busy (IOBUS.sub.-- BSY-) signal to indicate to all of the processors that the I/O bus is in use and that all other I/O requests must be held until the current transaction is completed. By preventing the other processors from executing an I/O request, the system bus does not have to be remain idle and can be used for memory-to-processor and for processor-to-processor transactions while the I/O bus is in use. By reducing the amount of time that the system bus is idle, the overall system bus performance is greatly increased.

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