Microprocessor with an interruptable bus cycle

Details Microprocessor with an interruptable bus cycle Microprocessor with an interruptable bus cycle

1985-05-30

1989-04-04

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 100

Patent

active

048191582

ABSTRACT:
In a semiconductor integrated circuit, an internal logic circuit outputs information for an external bus via buffer circuits. The output of the buffer circuit is placed in a high impedance state by responding to a control signal, and the information which is output from the internal logic circuit to the buffer circuits is held in the bus cycle during which the control signal is input. In the response to a release of the control signal by the input of the control signal, the interrupted bus cycle is released, and the information stored is output via the buffer circuit to the external bus.

REFERENCES:
patent: 4112490 (1978-09-01), Pohlman et al.
patent: 4240138 (1980-12-01), Chauvel
patent: 4458313 (1984-07-01), Suzuki et al.
patent: 4488228 (1984-12-01), Crudele et al.
patent: 4602327 (1986-07-01), LaViolette
patent: 4720811 (1988-01-01), Yamaguchi et al.

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