Self-correcting memory system

Details Self-correcting memory system Self-correcting memory system

1979-12-19

1982-03-09

Malzahn, David H.

Excavating

371 13, G06F 1110

Patent

active

043193560

ABSTRACT:
A self-correcting memory system includes internal error detection and correction circuitry that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system. The error detection and correction circuitry includes an ECC checking circuit that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter is cascaded to a refresh address counter in the control circuitry of the memory system so that the accessing of each data word occurs during a refresh cycle of the memory system.

REFERENCES:
patent: 3573728 (1971-04-01), Kolankowsky
patent: 3989894 (1976-11-01), Charransol et al.
patent: 4183096 (1980-01-01), Cenker et al.
patent: 4216541 (1980-08-01), Clover et al.
patent: 4255808 (1981-03-01), Schaber

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