Integrated semiconductor device comprising multi-layer circuit e

Details Integrated semiconductor device comprising multi-layer circuit e Integrated semiconductor device comprising multi-layer circuit e

1975-03-21

1976-12-21

Wojciechowicz, Edward J.

357 40, 357 47, 357 52, 357 86, H01L 2704, H01L 2702, H01L 2934

Patent

active

039992152

ABSTRACT:
An integrated circuit having multi-layer transistors which are separated from each other by means of tub-shaped or dish-shaped isolation zones. The isolation zones are of a conductivity type opposite to that of the zone of the circuit element which adjoins the inner wall of the tub-shaped zone and is present within the isolation zone, the p-n junction between the last-mentioned zone and the isolation zone being substantially short-circuited. As a result of this it is substantially prevented that the adjoining zone of the circuit element injects, via said p-n junction, charge carriers into the isolation zone, as a result of which the isolation is improved inter alia in that sense that the leakage current is reduced and higher breakdown voltages and smaller stray capacitances occur.

REFERENCES:
patent: 3283170 (1966-11-01), Buie
patent: 3474308 (1969-10-01), Kronlage
patent: 3502951 (1970-03-01), Hunts
patent: 3517280 (1970-06-01), Rosier
patent: 3590345 (1971-06-01), Brewer et al.
patent: 3596149 (1971-07-01), Makimoto
patent: 3648130 (1972-03-01), Castrucci et al.

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