Semiconductor memory device and a driving method of the same

Details Semiconductor memory device and a driving method of the same Semiconductor memory device and a driving method of the same

1998-11-05

2000-05-23

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365 63, 36523006, G11C 800

Patent

active

060672714

ABSTRACT:
For preventing skews between connecting timing of local I/O lines to global I/O lines and that to bit lines and reducing chip size as well, a semiconductor memory device, having a plurality of banks (10a and 10b) each comprising a plurality of sub-arrays (20) arranged in matrix, global I/O-line pairs (40) extending in a y-direction traversing the banks (10a and 10b) and each shared by two columns of the sub-arrays (20), local I/O-line pairs (30) extending in a x-direction and each traversing sub-arrays (20) of each row of the two columns, and column-selection lines (33) extending in the y-direction traversing the sub-arrays of columns of each of the banks (10a and 10b) for selecting bit-line pairs (34) to be connected to the local I/O-line pairs, comprises I/O switch lines (60), whereof each is extending along with each of the global I/O-line pairs in each of the banks (10a and 10b), for transmitting a column-activating signal for connecting the global I/O-line pairs (40) to the local I/O-line pairs (30) of a row of the sub-arrays (20) to be accessed. The local I/O-line pairs (30) are connected to the global I/O-lines (40) according to AND logic of the column-activating signal and row-activating signal for activating the row of the sub-arrays to be accessed.

REFERENCES:
patent: 5675529 (1997-10-01), Poole
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5923605 (1999-07-01), Mueller et al.
patent: 5930196 (1999-07-01), Yim

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