Delay lock loop circuit for semiconductor memory device

Details Delay lock loop circuit for semiconductor memory device Delay lock loop circuit for semiconductor memory device

1998-04-24

2000-05-23

Zweizig, Jeffrey

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327117, 327165, 327172, 327294, H03L 706

Patent

active

060669683

ABSTRACT:
A delay lock loop circuit for a semiconductor memory element generates a synchronized internal clock signal by receiving an external clock signal as an input. The delay lock loop circuit generates a clock signal having a very fast period in order to enhance speed of data being synchronized by a clock signal. The delay lock loop (DLL) circuit includes: a N frequency dividing means which respectively receives the external signal having the frequency f, and generates a signal having a frequency f/N; a N delay lock loop means which respectively receives the signal having the frequency f/N generated from the N frequency dividing means, and maintains it for a predetermined period; and a merging means which performs a logic operation on each output pulse signal generated from the N delay lock loop means, and generates the synchronised internal signal.

REFERENCES:
patent: 4754163 (1988-06-01), Aue et al.
patent: 5369311 (1994-11-01), Wang et al.

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