Static information storage and retrieval – Addressing
Patent
1984-05-29
1987-06-09
Fears, Terrell W.
Static information storage and retrieval
Addressing
365189, G11C 1300
Patent
active
046725873
ABSTRACT:
A monolithically integratable transmission system for binary information has at least one address source which is connected to at least one address sink via an address bus. The address sink is respectively allocated to a register means connected to a data bus. A clock generator generates a first clock signal and a non-overlapping, phase-shifted second clock signal. The address bus and the data bus are precharged during the first clock signal and access of an addressed register means to the data bus occurs during the second clock signal. In the time span between the two clock signals, the address bus is charged with the address signals by discharging.
REFERENCES:
IBM Technical Disclosure Bulletin entitled "Data Bus Precharge", J. C. Hsieh, Nov. 1975, vol. 18, No. 6, pp. 1871-1872.
Siemens-SAB 8048 8 Bit Single Chip Microcomputer Sep., 1982.
Geiger Gerhard
Strafner Michael
Fears Terrell W.
Siemens Aktiengesellschaft
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