Hierarchically connected reconfigurable logic assembly

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364488, H03K 17735, G06F 1750

Patent

active

054522315

ABSTRACT:
A plurality of electronically reconfigurable gate array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected circuits. The reconfigurable interconnect permits the digital network realized on the interconnected circuits to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA circuits dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic circuits. Other reconfigurable interconnect topologies are also detailed. If desired, the logic circuits and interconnect can be implemented in wafer-scale technology. Hybrid simulation employing both an ERCGA hardware simulator and a second simulator permits intermediate states of a circuit's operation to be reached quickly and analyzed in detail.

REFERENCES:
patent: 3106698 (1963-10-01), Unger
patent: 3287702 (1966-11-01), Borck, Jr. et al.
patent: 3287703 (1966-11-01), Slotnick
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4020469 (1977-04-01), Manning
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4386403 (1983-05-01), Hsieh et al.
patent: 4488354 (1984-12-01), Chan et al.
patent: 4503386 (1985-03-01), DasGupta et al.
patent: 4541071 (1985-09-01), Ohmori
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4578761 (1986-03-01), Gray
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4612618 (1986-09-01), Pryor et al.
patent: 4621339 (1986-11-01), Wagner et al.
patent: 4642487 (1987-01-01), Carter
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 4656592 (1987-04-01), Spaanenburg et al.
patent: 4675832 (1987-06-01), Robinson et al.
patent: 4682440 (1988-11-01), Nomizu et al.
patent: 4695999 (1987-09-01), Lebizay
patent: 4697241 (1987-09-01), Lavi
patent: 4700187 (1987-10-01), Furtek
patent: 4706216 (1987-11-01), Carter
patent: 4722084 (1988-01-01), Morton
patent: 4736338 (1988-04-01), Saxe et al.
patent: 4740919 (1988-04-01), Elmer
patent: 4744084 (1988-05-01), Beck et al.
patent: 4747102 (1988-05-01), Funatsu
patent: 4752887 (1988-06-01), Kuwahara
patent: 4758985 (1988-07-01), Carter
patent: 4768196 (1988-08-01), Jou et al.
patent: 4777606 (1988-10-01), Fournier
patent: 4786904 (1988-11-01), Graham, III et al.
patent: 4787061 (1988-11-01), Nei et al.
patent: 4791602 (1988-12-01), Resnick
patent: 4803636 (1989-02-01), Nishiyama et al.
patent: 4811214 (1989-03-01), Nosenchuck et al.
patent: 4815003 (1989-03-01), Patatunda et al.
patent: 4823276 (1989-04-01), Hiwatashi
patent: 4827427 (1989-05-01), Hyduke
patent: 4835705 (1989-05-01), Fujino et al.
patent: 4849904 (1989-07-01), Aipperspach et al.
patent: 4849928 (1989-07-01), Hauck
patent: 4862347 (1989-08-01), Rudy
patent: 4870302 (1989-09-01), Freeman
patent: 4876466 (1989-10-01), Kondou et al.
patent: 4882690 (1989-11-01), Shinsha et al.
patent: 4901259 (1990-02-01), Watkins
patent: 4901260 (1990-02-01), Lubachevsky
patent: 4908772 (1990-03-01), Chi
patent: 4914612 (1990-04-01), Beece et al.
patent: 4918440 (1990-04-01), Furtek
patent: 4918594 (1990-04-01), Onizuka
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4924429 (1990-05-01), Kurashita et al.
patent: 4931946 (1990-06-01), Ravindra et al.
patent: 4935734 (1990-06-01), Austin
patent: 4942536 (1990-07-01), Watanabe et al.
patent: 4942615 (1990-07-01), Hirose
patent: 4945503 (1990-07-01), Takasaki
patent: 4949275 (1990-08-01), Nonaka
patent: 4951220 (1990-08-01), Ramacher et al.
patent: 4965739 (1990-10-01), Ng
patent: 5003487 (1991-03-01), Drumm et al.
patent: 5023775 (1991-06-01), Poret
patent: 5041986 (1991-08-01), Tanishita
patent: 5046017 (1991-09-01), Yuyama et al.
patent: 5051938 (1991-09-01), Hyduke
patent: 5053980 (1991-10-01), Kanazawa
patent: 5081602 (1992-01-01), Glover
patent: 5084824 (1992-01-01), Lam et al.
patent: 5093920 (1992-03-01), Agrawal et al.
patent: 5109353 (1992-04-01), Sample et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5231588 (1993-07-01), Agrawal et al.
patent: 5231589 (1993-07-01), Itoh et al.
patent: 5233539 (1993-08-01), Agrawal et al.
"The Homogenous Computational Medium: New Technology For Computation", Concurrent Logic, Inc., Jan. 26, 1987.
Spandorfer, "Synthesis of Logic Functions on an Array of Integrated Circuits", Contract Report AFCRI-66-298, Oct. 31, 1965.
Tham, "Parallel Processing CAD Applications", IEEE Design & Test of Computer, Oct. 1987, pp. 13-17.
Agrawal et al, "MARS: A Multiprocessor-Based Programmable Accelerator", IEEE Design & Test of Computers, Oct. 1987, pp. 28-36.
Manning, "An Approach to Highly Integrated, Computer-Maintained Cellular Arrays", IEEE Transactions on Computers, vol. C-26, No. 6, Jun. 1977, pp. 536-552.
Manning, "Automatic Test, Configuration, and Repair of Cellular Arrays", Doctoral Thesis MAC TR-151 (MIT), Jun. 1975.
Shoup, "Programmable Cellular Logic Arrays," Doctoral Thesis (Carnegie-Mellon University; DARPA Contract No. F44620-67-C-0058), Mar. 1970.
Shoup, "Programmable Cellular Logic," undated, pp. 27-28.
Wynn, "In-Circuit Emulation for ASIC-Based Designs," VLSI Systems Design, Oct. 1986, pp. 38-45.
Minnick, "Survey of Microcellular Research," Stanford Research Institute Project 5876 (Contract AF 19(628)-5828), Jul. 1966.
Minnick, "A Programmable Cellular Array," undated, pp. 25-26.
Minnick, "Cutpoint Cellular Logic," IEEE Transactions On Electronic Computers, Dec. 1964, pp. 685-698.
Jump et al, "Microprogrammed Arrays," IEEE Transactions on Computers, vol. C-21, No. 9, Sep. 1972, pp. 974-984.
Gentile et al, "Design of Switches for Self-Reconfiguring VLSI Array Structures," Microprocessing and Microprogramming, North-Holland, 1984, pp. 99-108.
Sami et al, "Reconfigurable Architectures for VLSI Processing Arrays," AFIPS Conference Proceedings, 1983 National Computer Conference, May 16-19, 1983, pp. 565-577.
Kautz et al, "Cellular Interconnection Arrays," IEEE Transactions On Computers, vol. C-17, No. 5, May 1968, pp. 443-451.
Krautz, "Cellular Logic-in-Memory Arrays," IEEE Transactions On Computers, vol. C-18, No. 8, Aug. 1969, pp. 719-727.
Synder, "Introduction to the Configurable, Highly Parallel Computer," Report CSD-TR-351, Office of Naval Research Contracts N00014-80-K-0816 and N00014-81-K-0360, Nov. 1980.
Chen, "Fault-Tolerant Wafer Scale Architectures Using Large Crossbar Switch Arrays," excerpt from Jesshope et al, Wafer Scale Integration, Adam Hilger, 1986, pp. 113-124.
Kung, "Why Systolic Architectures?," Computer, Jan. 1982, pp. 37-46.
Hedlund, "Wafer Scale Integration of Parallel Processors," Doctoral Thesis (Purdue University; Office of Naval Research Contracts N00014-80-K-0816 and N00014-81-K-0360), 1982.
Hedlund et al, "Systolic Architectures-A Wafer Scale Approach," IEEE, 1984, pp. 604-610.
Choi et al, "Fault Diagnosis of Switches In Wafer-Scale Arrays," AIEEE, 1986, pp. 292-295.
Beece et al, "The IBM Engineering Verification Engine," 25th ACM/IEEE Design Automation Conference, Paper 17.1, 1988, pp. 218-224.
Pfister, "The Yorktown Simulation Engine: Introduction," 19th Design Automation Conference, Paper 7.1, 1982, pp. 51-54.
Denneau, "The Yorktown Simulation Engine," 19th Design Automation Conference, Paper 7.2. 1982, pp. 55-59.
Kronstadt et al, "Software Support for the Yorktown Simulation Engine," 19th Design Automation Conference, Paper 7.3, 1982, pp. 60-64.
Koike et al, "HAL: A High-Speed Logic Simulation Machine," IEEE Design & Test, Oct. 1985, pp. 61-73.
Shear, "Tools help you retain the advantages of using breadboards in gate-array design," EDN, Mar. 18, 1987, pp. 81-88.
McClure, "PLD Broadboarding of Gate Array Designs," VLSI Systems Design, Feb. 1987, pp. 36-41.
Anderson, "Restructurable VLSI Program" Report No. ESD-TR-80-192 (DARPA Contract No. F19628-80-C-0002), Mar. 31, 1980.
"The Programmable Gate Array Design Handbook," First Edition Xilinx, 1986, pp. 1-1 to 4

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Hierarchically connected reconfigurable logic assembly does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Hierarchically connected reconfigurable logic assembly, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Hierarchically connected reconfigurable logic assembly will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1833731

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.