MIS type semiconductor device formed in a semiconductor substrat

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357 2311, 357 52, H01L 2702

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active

051287390

ABSTRACT:
In order to provide semiconductor devices having a high switching speed and high packing density of the circuit elements, a p-MOSFET of a CMOS IC is formed on an n-type well which has a higher impurity concentration compared with that of the n-type substrate region and which is formed at selected portions under the p-MOSFET. In order to decrease the capacitance of the source and drain of the p-MOSFET, the n-type well regions are selectively formed only at portions under the gate electrode and the field insulating layer, and a junction of the p.sup.+ -type drain and source region is formed directly on a part of the n.sup.- -type substrate region. As a result, the latch-up phenomenon can be suppressed and the junction capacitance of the devices becomes smaller. Therefore, the switching speed and the packing density of the CMOS IC are improved.

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European Search Report, the Hague, Aug. 12, 1985, Examiner: D. L. D. Morvan.

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