Static random access memory cell using a P/N-MOS transistors

Details Static random access memory cell using a P/N-MOS transistors Static random access memory cell using a P/N-MOS transistors

1990-06-13

1992-07-07

Hille, Rolf

357 237, 357 42, H01L 2978

Patent

active

051287315

ABSTRACT:
A P/N-MOS transistor having source and drain of opposite semiconductor types is provided. One embodiment of the P/N-MOS transistor has turn-off characteristic similar to a PMOS transistor, and turn-on characteristic similar to a PMOS transistor connected in series with a p-n junction diode. An application of the P/N-MOS transistor is provided in a static random access memory (SRAM) cell. This SRAM cell has density advantage over SRAM cells using polysilicon PMOS transistors as active transistors.

REFERENCES:
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IEEE Transaction on Electron Devices, vol. ED-32, No. 2, Feb. 1985, "Characteristics and Three-Dimensional Integration of MOSFET's in Small-Gain LPCVD Polycrystalline Silicon" by Malhi et al.
H. Shichiojo, et al., "Polysilicon Transistors in VLSI MOS Memories," IEDM pp. 228-231, 1984.
T. Yamanaka et al., "A 25 UM2 New Poly-Si PMOS Load (PPL) SRAM Cell having Excellent Soft Error Immunity," IEDM, pp. 48-51, 1984.
M. Ando et al., "A 0.1-uA Standby Current, Ground-Bounce-Immune 1-Mbit CMOS SRAM," IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 89, pp. 1708-1713.

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