Method of making a dynamic random access memory cell with stacke

Details Method of making a dynamic random access memory cell with stacke Method of making a dynamic random access memory cell with stacke

1990-06-12

1992-07-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437919, H01L 2170

Patent

active

051282739

ABSTRACT:
A DRAM device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.

REFERENCES:
patent: 4715015 (1987-12-01), Mimoto et al.
patent: 4742018 (1988-05-01), Kimura et al.
Patent Abstracts of Japan, vol. 11, No. 376 (E-563) (2823), Dec. 8, 1987; JP-A-62 145 765 (Hitachi Ltd.).
Patent Abstracts of Japan, vol. 9, No. 31 (E-295) (1754), Feb. 9, 1985; JP-A-59 175 153 (Nippon Kenki K.K.).
Patent Abstracts of Japan, vol. 9, No. 106 (E-313) (1829), May 10, 1985l & JP-A-59 231 851 (Nippon Denshin Denwa Kosha).
IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, "A 5-V Only 16-KBit Stacked-Capacitor MOS RAM", M. Koyangi et al., pp. 661-666.

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