Partial width stalls within register alias table

Details Partial width stalls within register alias table Partial width stalls within register alias table

1993-12-29

1995-08-29

Coleman, Eric

395375, G06F 1578

Patent

active

054469120

ABSTRACT:
A partial width stall mechanism within a register alias table unit (RAT) for handling partial width data dependencies of a given set of operations issued simultaneously within a superscalar microprocessor. Operations of the given set are presented to the RAT in program order and partial width data dependencies occur when the size of a logical source register that is presented to the RAT for renaming to a corresponding physical source register is larger than the corresponding physical source register selected by the RAT. At this occurrence, the data required by the logical source register to be renamed does not reside in any one physical source register. Therefore, renaming of that logical register must be stalled until the data for that logical register is accumulated into one location. The data will be so accumulated when the last operation to have written the physical source register is retired and is, therefore, nonspeculative. The present invention includes a size comparison mechanism to detect the partial width stall condition. Also included is a partial width stall mechanism for preventing the renaming process from operating when the partial width stall condition is detected. In general the RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set to eliminate false data dependencies that would otherwise reduce overall superscalar processing performance for the microprocessor.

REFERENCES:
patent: 4901233 (1990-02-01), Liptay
patent: 4903196 (1990-02-01), Pomerenee et al.
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5197132 (1993-03-01), Steely, Jr. et al.
Sohi; "Instruction Issue Logic for High-Performance Interrupible Multiple Functional Unit, Pipelined Computer"; IEEE, Mar. 1990.
"Vector Register Allocation", Apr. 1990, IBM TBS.
Uvieghara et al., "An Experimental Single Chip Data Flow CPU"; IEEE; 1990.
Uvieghara et al., "An On-Chip Smart Memory for Data-Flow CPU"; IEEE; 1990.
Butter et al., "An Area-Efficient Register Alias Table for Implementing HPS"; IEEE; Apr. 1990.
Gwennap; "NexGen Enters Market with 66-MHz Nx 586"; Microprocessor Report, Mar. 1994.
Gwemap; "Intel, HPally on New Processor Architecture"; Microprocessor Report; Jun. 1994.
Val Popescu, et al. entitled, "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. 10-13, 63-73.
Author, Mike Johnson, entitled Superscalar Microprocessor Design, Advance Micro Devices, Prentice Hall Series in Innovative Technology, 1991, pp. 1-289.
"PA7200: A PA-RISC Processor with Integrated High Performance MP Bus Interface", Kurpanek, et al., pp. 375-382, 1994 IEEE, Hewlett-Packard Company.

Affiliated with

Also associated with

Rating

Partial width stalls within register alias table does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Partial width stalls within register alias table, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Partial width stalls within register alias table will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1827577