1990-01-03
1992-02-18
Hille, Rolf
357 233, 357 238, 357 239, 357 67, 357 59, H01L 2910, H01L 2978, H01L 2904
Patent
active
050898655
ABSTRACT:
In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.
REFERENCES:
patent: 4690730 (1987-09-01), Tang et al.
patent: 4894694 (1990-01-01), Cham et al.
patent: 4949136 (1990-08-01), Jain
Ryuichi Izawa et al., "The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's", IEDM 87 (1987) pp. 38-41.
Inuishi masahide
Mitsui Katsuyoshi
Hille Rolf
Mitsubishi Denki & Kabushiki Kaisha
Potter Roy
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