Patent
1990-09-10
1992-02-18
Hille, Rolf
357 37, 357 38, 357 39, H01L 2978
Patent
active
050898647
ABSTRACT:
This invention relates to an insulated gate type semiconductor device having an increased breakdown endurance capacity. According to the present invention, by decreasing the space between base regions or increasing the widths of adjacent base regions of cells near a connecting conductor fixed portion of a common emitter electrode of an IGBT or a common source electrode of an insulated gate type MOSFET so that the ratio between both falls within the range of 0.2 to 0.4, it is possible to suppress the latch-up phenomenon or the latch-back phenomenon which is liable to occur because of a local temperature rise caused by concentration of electric current. Furthermore, it is possible to limit the increase of the forward voltage drop in that case to within a range that does not inhibit practical use of the device . With this, either latch-up endurance capacity, in the case of a IGBT, or latch-back endurance capacity, in the case of an insulated gate type MOSFET, is improved.
REFERENCES:
patent: 4466176 (1984-08-01), Temple
patent: 4618872 (1986-10-01), Baliga
patent: 4682195 (1987-07-01), Yilmaz
patent: 4689647 (1987-08-01), Nakagawa et al.
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patent: 4809045 (1989-02-01), Yilmaz
patent: 4928155 (1990-05-01), Nakagawa et al.
IEEE Transactions on Electron Devices, vol. ED-31, No. 12, Dec. 1984, "Optimum Design of Power MOSFET's" by Hu et al, pp. 1693-1700.
Fuji Electric & Co., Ltd.
Hille Rolf
Loke Steven
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