Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1987-11-18

1989-01-31

Popek, Joseph A.

Static information storage and retrieval

Addressing

365233, G11C 800

Patent

active

048021326

ABSTRACT:
A semiconductor memory device includes a memory cell array having N memory blocks; N buffers respectively connected to the memory blocks; drivers, data selection circuits for selecting data to or from the drivers, a plurality of data buses connected to the data selection circuits, and a control unit for supplying control signals to said data selection circuits in each operation cycle, causing the data buses to be sequentially connected to the drivers via the data selection circuits, thereby permitting serial data to be transferred with respect to the memory cell array means via the data buses. The buffers are divided into n groups, n buffer selection circuits are each connected between a corresponding one of groups of the buffers and a corresponding one of the data buses, and the control unit supplies control signals to the buffer selection circuits, causing one of the buffers to be selectively connected to a corresponding one of the data buses via a corresponding one of the buffer selection circuits, and causing the data buses to be sequentially connected to the drivers via the data selection circuits, thereby permitting serial data to be transferred with respect to the memory cell array via the data buses.

REFERENCES:
patent: 4562555 (1985-12-01), Ouchi et al.
patent: 4685088 (1987-08-01), Fannucci
Takasugi, et al., "A Data-Transfer Architecture For Fast Multi-Bit Serial Access Mode DRAM," ESSCIRC'85 11th European Solid-State Circuits Conference, pp. 161-165, Sep. 16-18, 1985.

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