Polycide gate MOSFET process for integrated circuits

Details Polycide gate MOSFET process for integrated circuits Polycide gate MOSFET process for integrated circuits

1990-08-17

1992-02-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 44, 437 34, H01L 21264

Patent

active

050894323

ABSTRACT:
A method for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the problems in prior ICs. The method begins by forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and an amorphous refractory metal silicide. The resulting structure may be annealed in oxygen at this time to change the refractory metal silicide from it deposited amorphous phase into its crystalline phase. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric layer is blanket deposited over the surfaces. This layer is planned to form both the spacers and a cover layer for the refractory metal silicide layer. This is done by forming a lithography mask by conventional lithography and etching on the blanket layer and over the pattern of polycide gate electrode structures. RIE forms the spacer structure upon the sidewalls of each of the polycide gate structures and the cover layer. The lithography mask is removed. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The IC is completed by forming appropriate passivation/conductor layers to connect the elements.

REFERENCES:
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4690730 (1987-09-01), Tang et al.
patent: 4774201 (1988-09-01), Woo et al.
patent: 4994404 (1991-02-01), Sheng et al.

Affiliated with

Also associated with

Rating

Polycide gate MOSFET process for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Polycide gate MOSFET process for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Polycide gate MOSFET process for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1823238