1991-01-03
1993-06-01
Baker, Stephen M.
Excavating
G01R 3128, G11C 2900
Patent
active
052166732
ABSTRACT:
In a semiconductor memory tester in which a test pattern from a pattern generator is applied to a plurality of memory devices installed on a test head and their outputs are each logically compared by a logical comparator with an expected value for each pin, there are provided a plurality of OR circuits each of which obtains the OR of the results of logical comparisons corresponding to predetermined plural pins of each memory device. A plurality of multiplexers, each of which is supplied with the results of logical comparisons for corresponding output pins of the plurality of memory devices and a different one of the plurality of OR outputs, are provided for each group of corresponding output pins and each selectively output any one of the plurality of results of logical comparisons and the OR input thereto in accordance with a select signal. The outputs of these multiplexers are distributed to and stored in a plurality of fail memories.
REFERENCES:
patent: 4627053 (1986-12-01), Yamaki et al.
patent: 4860259 (1989-08-01), Tobita
patent: 5025205 (1991-06-01), Mydill et al.
M. W. Schraeder, "Multiplexed measuring devices reduce in-circuit-test expenses", May. 12, 1982, 2119 E.D.N. Electrical Design News, vol. 27 pp. 187-190, Boston, Mass.
Advantest Corporation
Baker Stephen M.
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