Method of forming a roughened surface capacitor with two etching

Fishing – trapping – and vermin destroying

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437 47, 437977, 437919, H01L 2170, H01L 2700

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054459869

ABSTRACT:
In a method of manufacturing a semiconductor device having a capacitor constituted by a lower electrode, an upper electrode, and a dielectric film arranged between the lower and upper electrodes, a polysilicon film containing a Group V element as an impurity is formed. The first etching step of forming an uneven portion on a surface of the polysilicon film is performed. The second etching step of forming an uneven portion on the surface of the polysilicon film is performed. The second etching step has an etch rate whose impurity concentration dependency is different from an impurity concentration dependency of an etch rate of the first etching step, thereby forming the uneven portion on the surface of the polysilicon film.

REFERENCES:
patent: 5068199 (1991-11-01), Sandhu
patent: 5134086 (1992-07-01), Ahn
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5286668 (1994-02-01), Chou
G. Q. Lo et al., "Highly Reliable SiO.sub.2 /Si.sub.3 N.sub.4 Stacked Dielectric on Rapid-Thermal-Nitrided Rugged Polysilicon for High-Density DRAM's", IEEE Electron Device Letters, vol. 13, No. 7, Jul. 1992, pp. 372-274.
Patent Abstracts of Japan, vol. 17, No. 241 (E-1364), May 14, 1993.

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