Parallel operating mode arithmetic logic unit apparatus

Details Parallel operating mode arithmetic logic unit apparatus Parallel operating mode arithmetic logic unit apparatus

1981-07-14

1983-11-22

Malzahn, David H.

Boots, shoes, and leggings

364785, G06F 750

Patent

active

044173148

ABSTRACT:
Apparatus is presented for logically combining two input signals in parallel operations to provide AND and OR as well as Exclusive OR outputs as part of the ALU function in a digital computer. The carry function is used in combination with the already generated signals of AND, OR and Exclusive OR to provide a carry output signal and a SUM signal through logic combining techniques. Thus, the entire ALU output is obtained in two stages of time delay and a great savings in components. In some computers, the outputs need to be passed through a four to one multiplexer to select the desired output.

REFERENCES:
patent: 3767906 (1973-10-01), Pryor
patent: 4229803 (1980-10-01), Rhodes
patent: 4263660 (1981-04-01), Prioste
patent: 4349888 (1982-09-01), Smith

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