Method of producing integrated MOS circuits via silicon gate tec

Details Method of producing integrated MOS circuits via silicon gate tec Method of producing integrated MOS circuits via silicon gate tec

1980-01-07

1982-02-02

Rutledge, L. Dewayne

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 148174, 148187, 156653, 156657, 156662, 204 15, 205325, 357 23, 357 59, H01L 2131, H01L 21441

Patent

active

043132561

ABSTRACT:
A method of producing integrated MOS circuits via silicon gate technology with self-adjusting contacts by using silicon nitride masking. In accordance with this method, after etching contact holes for the formation of contacts between monocrystalline doped regions (5) and polysilicon regions (4, 8), or metal interconnections (12), an insulating layer 10 is produced. This insulating layer is produced, after appropriate masking with an oxidation-inhibiting silicon nitride layer of the regions to be connected, from a layer (8) which is additionally applied and doped to correspond to the doped regions in the silicon substrate, and which is converted by local oxidation into the insulating layer (10). This process provides extremely high packing density of circuit elements.

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Rideout et al., "One-Device Memory Cell . . . Metal-to-Polysilicon Contact", Int. Electron Dev. Mtg., Tech. Digest, Wash. D.C., Dec. 1977, pp. 258-261.
Oldham et al., "Improved Integrated Circuit Contact Geometry using Local Oxidation", Proc. Electro Chem. Soc., Spring Mtg, Seattle, Wash., May 1978, pp. 690-691.

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