Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-01-12
1992-06-09
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307570, 307242, 340718, 340789, 340803, 340811, H03K 1716
Patent
active
051209918
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a driver circuit for converting a CMOS level signal to a high-voltage level and, more particularly, to a driver circuit for driving a flat panel display unit.
BACKGROUND ART
A flat panel display unit such as a plasma display is normally driven by a high voltage of about 100 V to 300 V. When such a flat panel display unit is controlled by a CMOS level signal having a logical amplitude of about 5 V, the unit cannot be directly driven by this logic signal. Therefore, a driver circuit for converting the CMOS level signal into a high-voltage level is required.
FIG. 7 is a circuit diagram showing the arrangement of a driver circuit used for the above purpose. This driver circuit possesses a function for determining the level of an output signal Out on the basis of an input signal In and a control signal cont. The circuit shown in FIG. 7 also has a function for setting the output state at a high-impedance state.
Referring to FIG. 7, reference numerals 51 to 54 denote double diffusion n-channel MOS transistors each having a structure of with a high withstand voltage; 55, a CMOS AND gate consisting of enhancement p- and n-channel MOS transistors; 56, an inverter; 57, a current setting resistor; 58, a pnp multicollector transistor; 59, a Zener diode for bias voltage generation; 60, an output terminal; and 61, a load capacitor corresponding to one segment of the flat panel display unit and connected to the output terminal 60. Reference symbol V.sub.DD denotes a power source voltage of, e.g., 5 V of a logical system; V.sub.CC, a power source voltage of, e.g., 300 V for a high-voltage system; and GND, a ground voltage of 0 V for the logical and high-voltage systems. The resistor 57 and the transistor 54 constitute a reference voltage generator 62 for generating a predetermined reference voltage Vref from the power source voltage V.sub.DD of the logical system. The reference voltage Vref, generated by the reference voltage generator 62, is supplied to the AND gate 55 as a power source voltage. The AND gate 55 also receives the input signal In and the control signal Cont. An output from the AND gate 55 is supplied to the gate of the transistor 53.
When both the input signal In and the control signal Cont are set at "1" level, an output signal from the AND gate 55 is also set at "1" level, i.e., at the reference voltage Vref. At this time, a drain current determined by the resistance of the resistor 57 and having the same value as that of the transistor 54 flows in the transistor 53. As a result, the multicollector transistor 58 is turned ON, and a predetermined Zener voltage appears at the cathode of the Zener diode 59 as a consequence of a current flowing out from one of the collectors of the multicollector transistor 58. If the value of the Zener voltage of the Zener diode 59 is set to the threshold voltage of the transistor 51 or higher, the transistor 51 is turned ON. Thus, when both the input signal In and the control signal Cont are set at "1" level, the output signal Out is set at "1" level, i.e., the V.sub.CC level, by means of the ON transistor 51.
However, when both the input signal In and the control signal Cont are set at "0" level, an output signal from the AND gate 55 is set at "0" level, and the transistor 53 is turned OFF. In this case, an output signal from the inverter 56 is set at "1" level, and then the transistor 52 is turned ON. As a result, the output terminal 60 is discharged through the Zener diode 59 and the ON transistor 52, and the output signal out is set at "0" level, i.e., the GND level.
When the input signal In is set at "1" level and the control signal Cont is set at "0" level, the transistors 51 and 52 are both turned OFF, and the output signal Out is set in a high-impedance state.
In the conventional circuit described above, the reference voltage Vref is always generated by the reference voltage generator 62 and a constant current flows therethrough. For this reason, however, when the output signal Out is to be set to "1" level, curre
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patent: 4458159 (1984-07-01), Konian
patent: 4678943 (1987-07-01), Uragami et al.
patent: 4851721 (1989-07-01), Okitaka
patent: 4942309 (1990-07-01), Chieli
L. Forbes, "Automatic On-Chip Threshold Voltage Compensation", IBM Technical Disclosure Bulletin, vol. 14, No. 10, Mar. 1972, pp. 2894-2895.
Kabushiki Kaisha Toshiba
Miller Stanley D.
Ouellette Scott A.
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