Silicide contact plug formation technique

Fishing – trapping – and vermin destroying

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Details

437192, 437246, 437228, 148DIG19, 357 71, H01L 21283

Patent

active

048187232

ABSTRACT:
An integrated circuit fabrication process for improving step coverage of the metal lines and of metal layer interconnections is disclosed. A conductive polysilicon, polycide, or polycide-on-polysilicon plug is formed in contact apertures by successive silicidation sequences of silicon/refractory metal deposition and heat treatment. A preceding silicide may also be removed prior to a succeeding silicidation to reduce silicon lining.

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patent: 4545852 (1985-10-01), Barton
patent: 4562640 (1986-01-01), Widmann et al.
patent: 4592802 (1986-06-01), Deleonibus et al.
Kircher et al, "Interconnection Method for ICs", IBM Tech. Disc. Bull., vol. 1, No. 2, Jul. 1970, p. 436.
Rideout, "Reducing the Sheet Resistance of Polysilicon Lines in ICs", IBM Tech. Disc. Bull., vol. 17, No. 6, Nov. 1974, pp. 1831-1833.
Murata et al, "Refractory Silicides of Ti and Ta . . . ", IEEE J of Solid State Circuits, vol. SC 15, No. 4, Aug. 1980, pp. 474-482.

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